In order to continue downscaling the size of transistors, their ‘architecture’ (the designed shape) has radically changed. Planar electron channels and gates are being replaced by vertical fin-shaped structures that are currently state-of-the-art, which will in the near-future be replaced by nanowires channels, with the gate materials wrapped all-around the channels for much better electrostatic control over the device switching. Microelectronic device fabrication comprises many processing steps, with controlled etching often being the critical step that determines the quality of the final transistor. Chemical wet-etching (post dry-etching) can be tuned to produce small diameter nanostructures with damage-free surfaces. However, wet-etching crystalline silicon can be challenging due to its non-isotropic etching behavior. In one crystal direction it etches faster than in the other. This is particularly unfortunate for the fabrication of nanoscale 3D structures in silicon, as is the case for the wire-shaped transistor channels for future gate-all-around (GAA) technology. This is a major hurdle that industry currently tries to overcome in order to be ready for fabricating future nodes of down-scaled devices. Anisotropic (directional) etching can give undesired results for transistor fabrication, such as faceted thinning of circular nanowires or nanopillars. Several approaches have been applied such as the use of metal impurities during etching, alcohols, light, pressure, microwave irradiation, corner compensation and ultrasonic irradiation etc. to alter the anisotropic wet-etching of c-Si2. All of these techniques have shown very limited control over anisotropy and none of them can switch the anisotropy completely at will.
TECHNOLOGY FEATURES & SPECIFICATIONS
We have developed a method for controlling the directionality of silicon we-etching. Single crystalline silicon (c-Si) nanopillar test structures are etched in potassium hydroxide (KOH) and tetra-methyl-ammonium hydroxide (TMAH) solution. The test structures are made on a 12-inch silicon-on-insulator (SOI) wafers and are suitable for future GAA technology. It is demonstrated that agitation of the etchant during wet-etching (for example by stirring it) plays a critical role in controlling the anisotropy of c-Si nanopillars that are etched in KOH solution. Stirred and non-stirred results show a 45º rotation in the etch anisotropy of c-Si i.e. a complete switching of the etch direction from the (110) and (100) crystallographic planes of silicon. On the other hand, no anisotropy switching is observed when samples are etched in TMAH solution using identical stirred and non-stirred conditions. By utilizing this controlled switching in etching direction, it is possible to maintain the circularity of the nanopillars while thinning them down to sub-10 nm diameter. By switching on and off of the sample stirring, the scaling down and miniaturization of channels size and overall device size are now made possible. No switching to another etchant for etching silicon in a different crystallographic direction is required.
The method of this invention solves a longstanding problem in microelectronic manufacturing. It provides a controlled and selective etching of semiconductors. Such control has in the past few years become particularly urgent due to the ongoing change in the design of microelectronic devices. The method disclosed is of great importance for the development of future microelectronic device fabrication of gate-all-around (GAA) and 3D silicon architectures.
The method of this invention enables circular silicon nanopillars with diameters as small as a few nanometers to be formed.