The demand for on-chip capacitor goes increasingly higher for integrated circuits (ICs) with 3D packaging technologies, because more capacitance-hungry chips are being stacked within a single IC package. However, huge surface area is required to implement those on-chip capacitors.
To address this issue, a novel method of embedding capacitors into through-substrate vias (TSVs) has been proposed. Instead of side-by-side placement, a TSV and a capacitor are now co-integrated into the same trench to leverage on the structure similarity of these two components. In this way, this invention boosts the capacitance density, and thus reduces the footprint of on-chip capacitors significantly
This technology can be implemented whereas TSVs are involved in IC packagings, e.g., 2.5D interposer, 3D Si substrate and fan-out molding. It brings in 10× higher capacitance density compared with that of conventional trench capacitor with the same design parameters. No degradation of leakage current and breakdown voltage need to be comprised.
On-chips capacitors can be used for a wide range of circuit applications:
The semiconductor industry is faced with a new trend of integrating more versatile devices, called “More than Moore” (MtM). It is certain that the demand for on-chip capacitors will increase explosively. At the same time, this MtM trend makes TSV a key enabler to interconnect chips vertically. The cost of TSV process keeps decreasing, as the it becomes more mature. The mass production of high bandwidth memory, involving thousands of TSVs, takes off in 2018. More design houses and foundries will be willing to adopt TSV in their products. This makes a great opportunity to use this invention to implement on-chip capacitors with superb capacitance density.
On-chip capacitors with small footprint will not only reduce the current manufacturing cost due to its reduced surface area, but also enable the potential integration of many other capacitance-hungry chips in 3D packagings.